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????????????????????????????????????????????????????????????????? maxim integrated products 1 general description the ds1308 serial real-time clock (rtc) is a low-power, full binary-coded decimal (bcd) clock/calendar plus 56 bytes of nv ram. address and data are transferred serially through an i 2 c interface. the clock/calendar provides seconds, minutes, hours, day, date, month, and year information. the end of the month date is auto - matically adjusted for months with fewer than 31 days, including corrections for leap year. the clock operates in either the 24-hour or 12-hour format with an am/pm indicator. the ds1308 has a built-in power-sense circuit that detects power failures and automatically switches to the backup supply, maintaining time and date operation. applications handhelds (gps, pos terminal) consumer electronics (set-top box, digital recording, network appliance) office equipment (fax/printer, copier) medical (glucometer, medicine dispenser) telecommunications (router, switcher, server) other (utility meter, vending machine, thermostat, modem) features s low timekeeping current of 250na (typ) s compatible with crystal esr up to 100k s rtc counts seconds, minutes, hours, date, month, day of the week, and year with leap-year compensation up to 2400 s 56-byte, battery-backed, general-purpose ram with unlimited writes s i 2 c serial interface s external clock source for synchronization clock reference (e.g., 32khz, 50hz/60hz powerline, gps 1pps) s programmable square-wave output signal s automatic power-fail detect and switch circuitry s -40 n c to +85 n c operating temperature range s underwriters laboratories (ul) recognized typical operating circuit 19-6353; rev 0; 5/12 ordering information appears at end of data sheet. for related parts and recommended products to use with this part, refer to: www.maxim-ic.com/ds1308.related ds1308 scl sda sqw/clkin x1 x2 v bat gnd v cc v cc r pu r pu r pu cpu v cc ds1308 low-current i 2 c rtc with 56-byte nv ram for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com.
????????????????????????????????????????????????????????????????? maxim integrated products 2 ds1308 low-current i 2 c rtc with 56-byte nv ram (all voltages relative to ground.) voltage range on v cc or v bat ........................... -0.3v to +6.0v voltage on any non-power pin ................ -0.3v to (v cc + 0.3v) operating temperature range .......................... -40 n c to +85 n c junction temperature maximum ..................................... +150 n c storage temperature range ............................ -55 n c to +125 n c lead temperature (soldering, 10s) ................................ +300 n c soldering temperature (reflow) ...................................... +260 n c absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional opera - tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions (t a = -40 n c to +85 n c, unless otherwise noted.) (note 2) dc electrical characteristics ( v cc = v ccmin to v ccmax , v bat = v batmin to v batmax , t a = -40 n c to +85 n c, unless otherwise noted.) (note 2) f sop junction-to-ambient thermal resistance ( b ja ) ..... 206.3 n c/w junction-to-case thermal resistance ( b jc ) ............... 42 n c/w note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four- layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial . package thermal characteristics (note 1) parameter symbol conditions min typ max units operating voltage range v cc ds1308-18 1.71 1.8 5.5 v ds1308-3 2.7 3.0 5.5 ds1308-33 3.0 3.3 5.5 battery voltage v bat 1.3 5.5 v logic 1 input v ih 0.7 x v cc v cc + 0.3 v logic 0 input v il -0.3 0.3 x v cc v parameter symbol conditions min typ max units power-supply active current (note 3) i cca -3 or -33: f scl = 400khz 325 f a power-supply standby current (note 4) i ccs -33: v cc = 3.63v 125 f a v cc = v ccmax 200 battery leakage current i batlkg v cc r v pf -100 25 +100 na input leakage (scl) i i v in = 0v to v cc -0.1 +0.1 f a i/o leakage (sda, sqw/clkin) i io i 2 c bus inactive, eclk = 1 -0.1 +0.1 f a output logic 0 (sda, sqw/ clkin), v ol = 0.4v i ol v cc r v ccmin 3.0 ma v bat r 1.3v r v cc + 0.2v 250 f a power-fail trip point v pf -33 2.70 2.82 3.00 v switchover voltage v sw v bat > v pf v pf v v bat < v pf v bat > v cc
????????????????????????????????????????????????????????????????? maxim integrated products 3 ds1308 low-current i 2 c rtc with 56-byte nv ram dc electrical characteristics ( v cc = 0v , v bat = v batmin to v batmax , t a = -40 n c to +85 n c, unless otherwise noted.) (note 2) ac electrical characteristics (v cc = v ccmin to v ccmax , t a = -40 n c to +85 n c, unless otherwise noted.) (note 2) parameter symbol conditions min typ max units battery current, sqw off (note 5) i bat1 v bat = 3v 250 na v bat = v batmax 600 battery current, sqw on (note 6) i bat2 v bat = 3v 550 na v bat = v batmax 1100 data-retention current (note 7) i batdat v bat = 3v 25 100 na parameter symbol conditions min typ max units scl clock frequency f scl (note 8) 0.03 400 khz bus free time between a stop and start condition t buf 1.3 f s hold time (repeated) start condition t hd:sta (note 9) 0.6 f s low period of scl clock t low 1.3 f s high period of scl clock t high 0.6 f s data hold time t hd:dat (notes 10, 11) 0 0.9 f s data setup time t su:dat (note 12) 100 ns setup time for a repeated start condition t su:sta 0.6 f s rise time of both sda and scl signals t r (note 13) 20 + 0.1c b 300 ns fall time of both sda and scl signals t f (note 13) 20 + 0.1c b 300 ns setup time for stop condition t su:sto 0.6 f s capacitive load for each bus line c b (note 13) 400 pf scl spike suppression t sp 60 ns oscillator stop flag (osf) delay t osf (note 14) 100 ms timeout interval t timeout (note 15) 25 35 ms
????????????????????????????????????????????????????????????????? maxim integrated products 4 ds1308 low-current i 2 c rtc with 56-byte nv ram power-up/down characteristics (t a = -40 n c to +85 n c, unless otherwise noted.) (notes 2, 16) capacitance (t a = +25 n c, unless otherwise noted.) (note 16) warning: negative undershoots below -0.3v while the part is in battery-backed mode may cause loss of data. note 2: limits are 100% production tested at t a = +25 n c and t a = +85 n c. limits over the operating temperature range and relevant supply voltage are guaranteed by design and characterization. typical values are not guaranteed. note 3: scl clocking at max frequency. v scl = 0v to v cc . note 4: specified with i 2 c bus inactive. timekeeping and square-wave functions operational. note 5: ch = eclk = sqwe = 0. note 6: ch = eclk = 0, sqwe = rs1 = rs0 = 1, i out = 0ma. note 7: ch = 1. eclk = sqwe = 0. note 8: the minimum scl clock frequency is limited by the bus timeout feature, which resets the serial bus interface if scl is held low for t timeout . note 9: after this period, the first clock pulse is generated. note 10: a device must internally provide a hold time of at least 300ns for the sda signal (referenced to the v ihmin of the scl signal) to bridge the undefined region of the falling edge of scl. note 11: the maximum t hd:dat has only to be met if the device does not stretch the low period (t low ) of the scl signal. note 12: a fast-mode device can be used in a standard-mode system, but the requirement t su:dat r to 250ns must then be met. this is automatically the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t rmax + t su:dat = 1000 + 250 = 1250ns before the scl line is released. note 13: c b is the total capacitance of one bus line, including all connected devices, in pf. note 14: the parameter t osf is the period of time the oscillator must be stopped for the osf flag to be set over the voltage range of 2.4v p v cc p v ccmax . note 15: the ds1308 can detect any single scl clock held low longer than t timeoutmin . the devices i 2 c interface is in reset state and can receive a new start condition when scl is held low for at least t timeoutmax . once the part detects this condition the sda output is released. the oscillator must be running for this function to work. note 16: guaranteed by design and not 100% production tested. parameter symbol min typ max units recovery at power-up t rec 1 2 ms v cc slew rate (v pf to 0v) t vccf 1/50 v/ f s v cc slew rate (0v to v pf ) t vccr 1/1 v/ f s parameter symbol min typ max units input capacitance c i 10 pf i/o capacitance c o 10 pf
????????????????????????????????????????????????????????????????? maxim integrated products 5 ds1308 low-current i 2 c rtc with 56-byte nv ram figure 1. data transfer on i 2 c serial bus figure 2. power-up/power-down timing scl note: timing is referenced to v ilmax and v ihmin . sda stop start repeated start t buf t hd:sta t hd:dat t su:dat t su:sto t hd:sta t sp t su:sta t high t r t f t low v cc scl sda valid recognized valid recognized v pf t vccf don?t care high impedance t rec t vccr
????????????????????????????????????????????????????????????????? maxim integrated products 6 typical operating characteristics (v cc = +3.3v, t a = +25 n c, unless otherwise specified.) power-supply current vs. scl frequency ds1308 toc05 scl frequency (khz) power-supply current (a) 300 200 100 100 150 200 50 0 400 t a = +25c, i out = 0ma 5.0v 3.0v sqw/clkin output-voltage low vs. output current ds1308 toc04 output current (ma) output voltage (v) 3 2 1 0.1 0.2 0.3 0.4 0 04 t a = +25c, out = eclk = sqwe = 0 v cc = 3.0v v cc = 5.0v v cc = 1.3v battery current (sqw on) vs. battery voltage ds1308 toc03 battery voltage (v) battery current (na) 4.5 3.5 2.5 300 400 500 600 700 800 200 1.5 5.5 rs1 = rs0 = sqwe = 1, i out = 0ma +85c +25c -40c battery current (sqw off) vs. battery voltage ds1308 toc02 battery voltage (v) battery current (na) 4.5 3.5 2.5 150 200 250 300 350 400 100 1.5 5.5 sqwe = 0, i out = 0ma +85c +25c -40c supply current vs. supply voltage ds1308 toc01 supply voltage (v) supply current (a) 5.0 4.5 3.5 4.0 80 90 100 110 130 120 140 150 70 3.0 5.5 sqwe = 1, i out = 0ma +85c +25c -40c ds1308 low-current i 2 c rtc with 56-byte nv ram
????????????????????????????????????????????????????????????????? maxim integrated products 7 ds1308 low-current i 2 c rtc with 56-byte nv ram pin configuration pin description pin name function 1 x1 32.768khz crystal connections. the internal oscillator circuitry is designed for use with a crystal having a specified load capacitance (c l ) of 6pf. note: for more information about crystal selection and crystal layout considerations, refer to application note 58: crystal considerations with maxim real-time clocks (rtcs) . 2 x2 3 v bat battery supply input for lithium cell or other energy source. battery voltage must be held between the minimum and maximum limits for proper operation. diodes placed in series between the backup source and the v bat pin can prevent proper operation. if a backup supply is not required, v bat must be grounded. ul recognized to ensure against reverse charging when used with a lithium cell. 4 gnd ground 5 sda serial data input/output for the i 2 c serial interface. it is an open-drain output and requires an external pullup resistor. the pullup voltage can be up to 5.5v, regardless of the voltage on v cc . 6 scl serial clock input for the i 2 c serial interface. used to synchronize data movement on the serial interface. the pullup voltage can be up to 5.5v, regardless of the voltage on v cc . 7 sqw/clkin square-wave output/clock input. this i/o pin is used to output one of four square-wave frequencies (1hz, 4khz, 8khz, 32khz) or accept an external clock input to drive the rtc counter. in the output mode (eclk = 0), it is open drain and requires an external pullup resistor. the square-wave operates on v cc , or on v bat with bbclk = 1. the pullup voltage can be up to 5.5v, regardless of the voltage on v cc . if not used, this pin may be left unconnected. 8 v cc primary power supply. decouple the power supply with a 0.1 f f capacitor to ground. sop 27 sqw/clkin x2 18 v cc x1 scl v bat 36 sda gnd 45 ds1308 top view +
????????????????????????????????????????????????????????????????? maxim integrated products 8 ds1308 low-current i 2 c rtc with 56-byte nv ram functional diagram detailed description the ds1308 serial rtc is a low-power, full bcd clock/ calendar plus 56 bytes of nv sram. address and data are transferred serially through an i 2 c interface. the clock/calendar provides seconds, minutes, hours, day, date, month, and year information. the end of the month date is automatically adjusted for months with fewer than 31 days, including corrections for leap year. the clock operates in either the 24-hour or 12-hour format with an am/pm indicator. the ds1308 has a built-in power-sense circuit that detects power failures and automatically switches to the v bat supply. operation the ds1308 operates as a slave device on the serial bus. access is obtained by implementing a start condition and providing a device identification code, followed by data. subsequent registers can be accessed sequen - tially until a stop condition is executed. the device is fully accessible and data can be written and read when v cc is greater than v pf . however, when v cc falls below v pf , the internal clock registers are blocked from any access. if v bat is greater than v bat , the device power is switched from v cc to v bat when v cc drops below v pf . if v bat is less than v pf , the device power is switched from v cc to v bat when v cc drops below v bat . the oscillator and timekeeping functions are maintained from the v bat source until v cc returns above v pf , read and write access is allowed after t rec. the functional diagram shows the main elements of the ds1308. an enable bit in the seconds register (ch) controls the oscillator. oscillator startup times are highly dependent upon crystal characteristics, pcb leakage, and layout. high esr and excessive capacitive loads are the major contributors to long startup times. a circuit using a crystal with the recommended characteristics and proper layout usually starts within 1 second. on the first application of power to the device, the time and date registers are reset to 01/01/00 01 00:00:00 (dd/ mm/yy dow hh:mm:ss), and ch bit in the seconds register is set to 0. ds1308 n n /4 /32 extsync control logic osc-1hz power control ram clock and calendar registers /2 128hz osc-1hz sqw/clkin x1 x2 scl sda 4.096khz 8.192khz 32.768khz mux/ buffer divider ext-1hz serial bus interface and address register v cc v bat
????????????????????????????????????????????????????????????????? maxim integrated products 9 ds1308 low-current i 2 c rtc with 56-byte nv ram freshness seal mode when a battery is first attached to the device, the device does not immediately provide battery-backup power to the rtc or internal circuitry. after v cc exceeds v pf , the devices leave the freshness seal mode and provide battery-backup power whenever v cc subsequently falls below v bat . this mode allows attachment of the battery during product manufacturing, but no battery capacity is consumed until after the system has been activated for the first time. as a result, minimum battery energy is used during storage and shipping. oscillator circuit the ds1308 uses an external 6pf 32.768khz crystal. the oscillator circuit does not require any external resistors or capacitors to operate. see table 2 for the external crystal parameters. the functional diagram shows a simplified schematic of the oscillator circuit. the startup time is usually less than 1 second when using a crystal with the specified characteristics. whenever v cc > v pf , a 5 f s glitch filter at the output of the crystal oscillator is enabled. clock accuracy the accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. crystal frequency drift caused by temperature shifts creates additional error. external circuit noise coupled into the oscillator circuit can result in the clock running fast. figure 3 shows a typical pcb layout for isolating the crystal and oscillator from noise. refer to application note 58: crystal considerations with maxim real-time clocks (rtcs) for detailed information. table 1. power control table 2. crystal specifications note: the crystal, traces, and crystal input pins should be isolated from rf generat - ing signals. refer to application note 58: crystal considerations for maxim real-time clocks (rtcs) for additional specifications. figure 3. typical pcb layout for crystal supply condition read/write access powered by v cc < v pf , v cc < v bat no v bat v cc < v pf , v cc > v bat no v cc v cc > v pf , v cc < v bat yes v cc v cc > v pf , v cc > v bat yes v cc parameter symbol min typ max units nominal frequency f o 32.768 khz series resistance esr 100 k i load capacitance c l 6 pf cr yst al x1 x2 gnd local ground plane (la yer 2) note: a void routing signals in the crossha tched area (upper left -hand quadrant) of the p ackage unless there is a ground plane between the signal line and the p ackage.
???????????????????????????????????????????????????????????????? maxim integrated products 10 ds1308 low-current i 2 c rtc with 56-byte nv ram rtc and ram address map table 3 shows the address map for the rtc and ram registers. the rtc registers and control register are located in address locations 00hC07h. the ram regis - ters are located in address locations 08hC3fh. during a multibyte access, when the register pointer reaches 3fh (the end of ram space) it wraps around to location 00h (the beginning of the clock space). on an i 2 c start, or register pointer incrementing to location 00h, the current time and date is transferred to a second set of registers. the time and date in the secondary registers are read in a multibyte data transfer, while the clock continues to run. this eliminates the need to re-read the registers in case of an update of the main registers during a read. clock and calendar the time and calendar information is obtained by reading the appropriate register bytes. the time and calendar are set or initialized by writing the appropriate register bytes. the contents of the time and calendar registers are in the bcd format. bit 7 of register 0 is the clock halt (ch) bit. when this bit is set to 1, the oscillator is disabled. when cleared to 0, the oscillator is enabled. the clock can be halted whenever the timekeeping functions are not required, which minimizes v bat current (i batdat ) when v cc is not applied. the day-of-week register increments at midnight. values that correspond to the day of week are user-defined but must be sequential (i.e., if 1 equals sunday, then 2 equals monday, and so on). illogical time and date entries result in undefined operation. when reading or writing the time and date registers, secondary (user) buffers are used to prevent errors when the internal registers update. when reading the time and date registers, the user buffers are synchronized to the internal registers on any start and when the register pointer rolls over to zero. the countdown chain is reset whenever the seconds register is written. write transfers occur on the acknowledge from the ds1308. once the countdown chain is reset, to avoid rollover issues the remaining time and date registers must be written within 1 second. the 1hz square-wave output, if enabled, transitions high 500ms after the seconds data transfer, provided the oscillator is already running. the ds1308 runs in either 12-hour or 24-hour mode. bit 6 of the hours register is defined as the 12-hour or 24-hour mode-select bit. when high, the 12-hour mode is selected. in the 12-hour mode, bit 5 is the am/pm bit, with logic high being pm. in the 24-hour mode, bit 5 is the 20-hour bit (20C23 hours). if the 12/24-hour mode select is changed, the hours register must be re-initialized to the new format. table 3. rtc and ram address map note: bits listed as 0 always read as a 0. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 function range 00h ch 10 seconds seconds seconds 00C59 01h 0 10 minutes minutes minutes 00C59 02h 0 12/24 am/pm 10 hour hour hours 1C12 +am/ pm 00C23 20 hour 03h 0 0 0 0 0 day day 1C7 04h 0 0 10 date date date 01C31 05h 0 0 0 10 month month month 01C12 06h 10 year year year 00C99 07h out eclk osf sqwe los bbclk rs1 rs0 control 08hC3fh ram 56 x 8 00hCffh
???????????????????????????????????????????????????????????????? maxim integrated products 11 ds1308 low-current i 2 c rtc with 56-byte nv ram control register (07h) the control register controls the operation of the sqw/clkin pin and provides oscillator status. bit 7: output control (out). controls the output level of the sqw/clkin pin when the square-wave output is disabled and v cc >v pf . if sqwe = 0, the logic level on the sqw/clkin pin is 1 if out = 1; it is 0 if out = 0. see table 4 . bit 6: enable clock input (eclk). this bit controls the direction of the sqw/clkin pin (see table 4 ). when eclk = 1, the sqw/clkin pin is an input, with the expected input rate defined by the states of rs1 and rs0. when eclk = 0, the sqw/clkin pin is an output, with the square-wave frequency defined by the states of rs1 and rs0. bit 5: oscillator stop flag (osf). a logic 1 in this bit indicates that the oscillator has stopped or was stopped for some time period and can be used to judge the validity of the clock and calendar data. this bit is edge triggered, and is set to logic 1 when the internal circuitry senses the oscillator has transitioned from a normal run state to a stop condition. the following are examples of conditions that may cause the osf bit to be set: the first time power is applied. the voltage present on v cc and v bat are insufficient to support oscillation. the ch bit is set to 1, disabling the oscillator. external influences on the crystal (i.e., noise, leakage, etc.). this bit remains at logic 1 until written to logic 0. this bit can only be written to logic 0. attempting to write osf to logic 1 leaves the value unchanged. bit 4: square-wave enable (sqwe). when set to logic 1, this bit enables the oscillator output to operate with either v cc or v bat applied. the frequency of the square-wave output depends upon the value of the rs0 and rs1 bits. bit 3: loss of signal (los). this status bit indicates the state of the clkin pin. the los bit is set to 1 when the rtc counter is no longer conditioned by the external clock. this occurs when 1) eclk = 0, or 2) when the clkin input signal stops toggling, or 3) when the clkin frequency differs by more than q 0.8% from the selected input frequency. this bit remains a 1 until written to 0. attempting to write los = 1 leaves the value unchanged. clearing the los flag when the clkin frequency is invalid inhibits subsequent detections of the input frequency deviation. bit 2: battery backup clock (bbclk). when set to logic 1, this bit enables the sqw/clkin i/o while the part is pow - ered by v bat . when set to logic 0, this bit disables the sqw/clkin i/o while the part is powered by v bat . bits 1 and 0: rate select (rs1 and rs0). these bits control the frequency of the sqw/clkin output when the square- wave has been enabled (sqwe = 1). table 4 lists the square-wave frequencies that can be selected with the rs bits. table 4. sqw/clkin pin functions x = dont care. bit # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name out eclk osf sqwe los bbclk rs1 rs0 por 1 0 1 1 1 1 1 1 out eclk sqwe rs1 rs0 sqw/clkin x 0 1 0 0 1hz output x 0 1 0 1 4.096khz output x 0 1 1 0 8.192khz output x 0 1 1 1 32.768khz output 0 0 0 x x 0 1 0 0 x x 1 x 1 x 0 0 1hz input x 1 x 0 1 50hz input x 1 x 1 0 60hz input x 1 x 1 1 32.768khz input
???????????????????????????????????????????????????????????????? maxim integrated products 12 ds1308 low-current i 2 c rtc with 56-byte nv ram external synchronization when an external clock reference is used, the input from sqw/clkin is divided down to 1hz. the 1hz from the divider (ext-1hz, see functional diagram ) is used to correct the 1hz that is derived from the 32.768khz oscil - lator (osc-1hz). as osc-1hz drifts in relation to ext-1hz, osc-1hz is digitally adjusted. as shown in the functional diagram , the three highest frequencies driving the sqw/clkin pin are derived from the uncorrected oscillator, while the 1hz output is derived from the adjusted osc-1hz signal. conceptually, the circuit can be thought of as two 1hz signals, one derived from the internal oscillator and the other from the external reference clock, with the oscillator-derived 1hz signal being locked to the 1hz signal derived from the external reference clock. the edges of the 1hz signals do not need to be aligned with each other. while the external clock source is present and within tolerance, the ext-1hz and osc-1hz maintain their existing lock, regardless of their edge alignment, with periodic correction of the osc-1hz signal. if the external signal is lost and then regained sometime later, the signals re-lock with whatever new alignment exists ( figure 4 ). the ext-1hz is used by the device as long as it is within tolerance, which is about 0.8% of osc-1hz. while ext-1hz is within tolerance, the skew between the two signals may shift until a change of about 7.8ms accumulates, after which osc-1hz signal is adjusted ( figure 5 ). the adjust - ment is accomplished by digitally adjusting the 32khz oscillator divider chain. figure 4. loss and reacquisition of external reference clock figure 5. drift adjustment of internal 1hz to external reference clock osc-1hz from oscilla tor ext -1hz from external reference skew skew break in external reference signal current lock shifted back to current lock drift after n cycles osc-1hz from oscilla tor ext -1hz from external reference
???????????????????????????????????????????????????????????????? maxim integrated products 13 ds1308 low-current i 2 c rtc with 56-byte nv ram if the difference between ext-1hz and osc-1hz is greater than about 0.8%, osc-1hz runs unadjusted (see figure 4 ) and the loss of signal (los) is set, provided the enable external clock input bit (eclk) is set. i 2 c serial port operation i 2 c slave address the ds1308s slave address byte is d0h. the first byte sent to the device includes the device identifier and the r/ w bit ( figure 6 ). the device address sent by the i 2 c master must match the address assigned to the device. i 2 c definitions the following terminology is commonly used to describe i 2 c data transfers. master device: the master device controls the slave devices on the bus. the master device generates scl clock pulses and start and stop conditions. slave devices: slave devices send and receive data at the masters request. bus idle or not busy: time between stop and start conditions when both sda and scl are inac - tive and in their logic-high states. when the bus is idle it often initiates a low-power mode for slave devices. start condition: a start condition is generated by the master to initiate a new data transfer with a slave. transitioning sda from high to low while scl remains high generates a start condition. see figure 1 for applicable timing. stop condition: a stop condition is generated by the master to end a data transfer with a slave. transitioning sda from low to high while scl remains high generates a stop condition. see figure 1 for applicable timing. repeated start condition: the master can use a repeated start condition at the end of one data transfer to indicate that it immediately initiates a new data transfer following the current one. repeated starts are commonly used during read operations to identify a specific memory address to begin a data transfer. a repeated start condition is issued identi - cally to a normal start condition. see figure 1 for applicable timing. bit write: transitions of sda must occur during the low state of scl. the data on sda must remain valid and unchanged during the entire high pulse of scl plus the setup and hold time requirements ( figure 1 ). data is shifted into the device during the rising edge of the scl. bit read: at the end a write operation, the master must release the sda bus line for the proper amount of setup time before the next rising edge of scl dur - ing a bit read ( figure 1 ). the device shifts out each bit of data on sda at the falling edge of the previous scl pulse and the data bit is valid at the rising edge of the current scl pulse. remember that the master generates all scl clock pulses including when it is reading bits from the slave. acknowledge (ack and nack): an acknowledge (ack) or not-acknowledge (nack) is always the 9th bit transmitted during a byte transfer. the device receiving data (the master during a read or the slave during a write operation) performs an ack by trans - mitting a zero during the 9th bit. a device performs a nack by transmitting a one during the 9th bit. timing for the ack and nack is identical to all other bit writes. an ack is the acknowledgment that the device is properly receiving data. a nack is used to terminate a read sequence or as an indication that the device is not receiving data. byte write: a byte write consists of 8 bits of informa - tion transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgment from the slave to the master. the 8 bits transmitted by the master are done according to the bit write definition and the acknowledgment is read using the bit read definition. byte read: a byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ack or nack from the master to the slave. the 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition, and the master transmits an ack using the bit write definition to receive additional data figure 6. slave address byte 11 1 0r /w 0 0 0 msb lsb read/ write bit device identifier
???????????????????????????????????????????????????????????????? maxim integrated products 14 ds1308 low-current i 2 c rtc with 56-byte nv ram bytes. the master must nack the last byte read to terminate communication so the slave returns control of sda to the master. slave address byte: each slave on the i 2 c bus responds to a slave address byte sent immediately following a start condition. the slave address byte contains the slave address in the most significant 7 bits and the r/ w bit in the least significant bit. the slave address is d0h and cannot be modified by the user. when the r/ w bit is 0 (such as in d0h), the mas - ter is indicating it writes data to the slave. if r/ w = 1, (d1h in this case), the master is indicating it wants to read from the slave. if an incorrect slave address is written, the ds1308 assumes the master is com - municating with another i 2 c device and ignores the communication until the next start condition is sent. memory address: during an i 2 c write operation, the master must transmit a memory address to identify the memory location where the slave is to store the data. the memory address is always the second byte transmitted during a write operation following the slave address byte. i 2 c communication writing a single byte to a slave: the master must generate a start condition, write the slave address byte (r/ w = 0), write the memory address, write the byte of data, and generate a stop condition. remember the master must read the slaves acknowl - edgment during all byte write operations. writing multiple bytes to a slave: to write multiple bytes to a slave, the master generates a start condi - tion, writes the slave address byte (r/ w = 0), writes the starting memory address, writes multiple data bytes, and generates a stop condition. reading a single byte from a slave: unlike the write operation that uses the specified memory address byte to define where the data is to be written, the read operation occurs at the present value of the memory address counter. to read a single byte from the slave, the master generates a start condition, writes the slave address byte with r/ w? = 1, reads the data byte with a nack to indicate the end of the transfer, and generates a stop condition. however, since requiring the mas - ter to keep track of the memory address counter is figure 7. i 2 c transactions sla ve address st ar t st ar t 1 1 0 1 0 0 0 sla ve ack slav e ack slav e ack r/w msb lsb msb lsb msb lsb b7 b6 b5 b4 b3 b2 b1 b0 read/ write register address b7 b6 b5 b4 b3 b2 b1 b0 da ta stop single byte write -write control register to bfh mul tibyte write -write da te register to "02" and month register to "11" single byte read -read control register mul tibyte read -read hours and da y register va lues st ar t repea ted st ar t d1h master nack stop 1 1010000 00000111 07h 1 1010001 1101000 0 0 000011 1 d0h 07h stop va lue st ar t 11010000 00000100 d0h 04h da ta master nack stop va lue da ta 02h bfh example i 2 c transactions typical i 2 c write transaction 10111111 00000010 d0h a) c) b) d) sla ve ack sla ve ack slav e ack sla ve ack sla ve ack sla ve ack slav e ack repea ted st ar t d1h master ack 1 1010001 va lue da ta slav e ack sla ve ack slav e ack st ar t 11010000 00000010 d0h 02h sla ve ack sla ve ack stop 11h 0001000 1 slav e ack
???????????????????????????????????????????????????????????????? maxim integrated products 15 ds1308 low-current i 2 c rtc with 56-byte nv ram impractical, the following method should be used to perform reads from a specified memory location. manipulating the address counter for reads: a dummy write cycle can be used to force the address counter to a particular value. to do this the mas - ter generates a start condition, writes the slave address byte (r/ w = 0), writes the memory address where it desires to read, generates a repeated start condition, writes the slave address byte (r/ w = 1), reads data with ack or nack as applicable, and generates a stop condition. see figure 7 for a read example using the repeated start condition to specify the starting memory location. reading multiple bytes from a slave: the read operation can be used to read multiple bytes with a single transfer. when reading bytes from the slave, the master simply acks the data byte if it desires to read another byte before terminating the transaction. after the master reads the last byte it must nack to indicate the end of the transfer and then it generates a stop condition. bus timeout to avoid an unintended i 2 c interface timeout, scl should not be held low longer than t timeoutmin . the i 2 c interface is in the reset state and can receive a new start condition when scl is held low for at least t timeoutmax . when the part detects this condition, sda is released and allowed to float. for the timeout function to work, the oscillator must be enabled and running. applications information power-supply decoupling to achieve the best results when using the ds1308, decouple the v cc power supply with a 0.01 f f and/or 0.1 f f capacitor. use a high-quality, ceramic, surface- mount capacitor if possible. surface-mount components minimize lead inductance, which improves performance, and ceramic capacitors tend to have adequate high- frequency response for decoupling applications. using open-drain outputs the sqw/clkin output is open drain and therefore requires an external pullup resistor to realize a logic-high output level. sda and scl pullup resistors sda is an open-drain output and requires an external pullup resistor to realize a logic-high output level. because the ds1308 does not use clock cycle stretch - ing, a master using either an open-drain output with a pullup resistor or cmos output driver (push-pull) could be used for scl. battery charge protection the ds1308 contains maxims redundant battery-charge protection circuit to prevent any charging of an external battery. handling, pcb layout, and assembly avoid running signal traces under the package, unless a ground plane is placed between the package and the signal line. the lead(pb)-free/rohs package can be soldered using a reflow profile that complies with jedec j-std-020. moisture-sensitive packages are shipped from the fac - tory dry-packed. handling instructions listed on the pack - age label must be followed to prevent damage during reflow. refer to the ipc/jedec j-std-020 standard for moisture-sensitive device (msd) classifications. chip information process: cmos substrate connected to ground ordering information package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. + denotes a lead(pb)-free/rohs-compliant package. * future productcontact factory for availability. part temp range pin-package DS1308U-18+* -40 n c to +85 n c 8 f sop ds1308u-3+* -40 n c to +85 n c 8 f sop ds1308u-33+ -40 n c to +85 n c 8 f sop package type package code outline no. land pattern no. 8 sop u8+1 21-0036 90-0092
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated, inc., 160 rio robles drive, san jose, ca 95134 408-601-1000 16 ? 2012 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 5/12 initial release ds1308 low-current i 2 c rtc with 56-byte nv ram

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